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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
SELF REFRESH Operation
Figure 59: Per-Bank REFRESH Operation
T0
T1
Tx
Tx + 1
Tx + 2
Ty
Ty + 1
Tz
Tz + 1
CK#
CK
CA[9:0]
AB
t RPab
t RFCpb
t RFCpb
Bank 1
Row A
Row A
CMD
PRECHARGE
NOP
NOP
REFpb
NOP
REFpb
NOP
ACTIVATE
NOP
REFRESH to bank 0
REFRESH to bank 1
ACTIVATE command
to bank 1
Notes:
1. Prior to T0, the REFpb bank counter points to bank 0.
2. Operations to banks other than the bank being refreshed are supported during the
t RFCpb period.
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the array, even if the rest of
the system is powered down. When in the self refresh mode, the device retains data
without external clocking. The device has a built-in timer to accommodate SELF RE-
FRESH operation. The SELF REFRESH command is executed by taking CKE LOW, CS#
LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock.
CKE must be HIGH during the clock cycle preceding a SELF REFRESH command. A
NOP command must be driven in the clock cycle following the SELF REFRESH com-
mand. After the power-down command is registered, CKE must be held LOW to keep
the device in self refresh mode.
Mobile LPDDR2 devices can operate in self refresh mode in both the standard and ex-
tended temperature ranges. These devices also manage self refresh power consumption
when the operating temperature changes, resulting in the lowest possible power con-
sumption across the operating temperature range. See Table 59 (page 115) for details.
After the device has entered self refresh mode, all external signals other than CKE are
“Don’t Care.” For proper self refresh operation, power supply pins (V DD1 , V DD2 , V DDQ ,
and V DDCA ) must be at valid levels. V DDQ can be turned off during self refresh. If V DDQ is
turned off, V REFDQ must also be turned off. Prior to exiting self refresh, both V DDQ and
V REFDQ must be within their respective minimum/maximum operating ranges (see the
Single-Ended AC and DC Input Levels for DQ and DM table). V REFDQ can be at any level
between 0 and V DDQ ; V REFCA can be at any level between 0 and V DDCA during self re-
fresh.
Before exiting self refresh, V REFDQ and V REFCA must be within specified limits (see AC
and DC Logic Input Measurement Levels for Single-Ended Signals (page 119)). After en-
tering self refresh mode, the device initiates at least one all-bank REFRESH command
internally during t CKESR. The clock is internally disabled during SELF REFRESH opera-
tion to save power. The device must remain in self refresh mode for at least t CKESR. The
user can change the external clock frequency or halt the external clock one clock after
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
82
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数
MT42L256M32D4KP-MS
制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk